1. Field Of The Invention
The present invention pertains to field programmable integrated circuits. More particularly, the present invention pertains to an interconnect architecture and the segmentation of conductors within that interconnect architecture.
2. The Prior Art
Routing channels in a field programmable gate array contain predefined wiring segments of various lengths. These may be permanently connected to the inputs and outputs of the gates or other functional circuitry on the integrated circuit or may be left uncommitted for use in routing. Pairs of adjacent wiring segments within a wiring track may be joined end-to-end to form longer segments by programmable interconnect elements. Such programmable interconnect elements may also be used to join wiring segments from different channels which cross over and under one another.
In mask programmable gate arrays, one or more metal layers are programmable, so segmentation can be customized for particular design. Segmentation schemes are thus unnecessary in such arrays because it is unnecessary to predefine segment lengths and positions.
With respect to user-configurable arrays, U.S. Pat. No. 4,758,745 discloses various aspects of segment length and offset. In addition, routing architectures in products made by Actel Corporation, the assignee of the present invention, Xilinx, Inc., and other companies are known to contain various length segments of conductors in the routing architecture.
Currently available user programmable integrated circuits utilize a limited variety of wiring segment lengths since additional segment length variety makes it more difficult to design and lay out the channels in the integrated circuit in a compact area. In addition, channels with a wide variety of segment lengths require the use of more complex and time consuming routing algorithms. This requirement becomes more difficult when connection of multiple adjacent short segments to create a longer segment is contemplated.
As the size and functionality of user-configurable integrated circuits increase and become more complex, the need for optimization of conductor segmentation for efficient routing becomes more important from both the stand points o circuit speeds and efficient use of silicon area. While the prior art known to the inventors has been useful for this purpose, there exists a significant speed and area penalty resulting from the need to connect together more wiring segments, or from use of segments having longer lengths, than would be needed in an optimized architecture.